1. Field of the Invention
The present invention relates to a semiconductor memory device requiring a refresh operation and in particular to data access control for reducing current consumption through a refresh operation in stand-by mode.
2. Description of the Related Art
In a semiconductor memory device requiring a refresh operation, such as a dynamic random access memory (called DRAM hereinafter), current to be charged/discharged to bit lines for sense amplifiers occupies a large ratio in the current consumption involved in access operations to memory cells. The access operations may be, for example, reading operation, writing operation and refresh operation. Thus, the reduction of current charged/discharged to bit lines has been attempted conventionally.
As one of those approaches to the current reduction, the reduction of the current consumption is being attempted by recycling and reusing the current charged/discharged to the bit lines. As one example, a charge recycling method disclosed in Japanese Laid-Open Patent Publication No. 8-249885 is shown in a circuit configuration diagram in FIG. 11 and an operational waveform diagram in FIG. 12.
FIG. 11 shows the disclosed circuit specification. Here, when VSS indicates a reference voltage, both drive lines SAP and /SAN of sense amplifiers are shorted by an equalizing signal (/EQL0 to /EQL(k−1)). Then, bit line pairs (BL0,/BL0 to BL(m−1),/BL(m−1)) are precharged to the (½)VCC. A large capacitor C2 having a potential voltage Vm2 between the VSS and (½)VCC precharge is connected between the sense amplifier drive line /SAN through a second switching element (SEN00 to SEN0(k−1)) and a power supply. Additionally, a large capacitor C1 having a potential voltage Vm1 between the VCC and the (½) VCC precharge is connected between the sense amplifier drive line SAP through a fourth switching element (/SEP00 to /SEP0(k−1)) and a power supply. Here, Vm1=(¾)VCC and Vm2=(¼) VCC are desirable voltage values.
FIG. 12 is an access operation example in the circuit configuration shown in FIG. 11. In FIG. 12, a cell array 0 is illustrated as an example. For a restore operation for rewriting charge to the memory cell, first of all, as an amplifying operation by the sense amplifier, the /SEP00 is turned to Low while the SEN00 is turned to High. Then, the SAP is coupled to Vm1 while the /SAN is coupled to Vm2. In this case, when a total sum of stray capacitance (as CB) for half of all bit lines within the cell array 0 satisfies C1>>CB and C2>>CB, the potential voltage of the SAP becomes Vm1 substantially, while the potential voltage of the /SAN becomes Vm2 substantially. In other words, the sense amplifier is driven between Vm1(=(¾)VCC) and Vm2(=(¼)VCC). Next, the /SEP00 and the SEN00 are returned to High and Low, respectively. Then, the /SEP10 and the SEN10 are turned to Low and High, respectively. The sense amplifier is driven between VCC voltage and VSS voltage so that VCC voltage is written in the memory cell.
For equalization, the /SEP10 and the SEN10 are returned to High and Low, respectively. Then, the /SEP00 and the SEN00 are turned to Low and High, respectively. It serves to return to capacitors C1 and C2 charges supplied from capacitors C1 and C2 to the bit lines at the time of the restoration. In other words, the recycling of charges are performed. After that, the /SEP00 and the SEN00 are returned to High and Low, respectively. Then, the /EQL0 is turned to High while the /SAN and the SAP are shorted.
With respect to each of the /SAN side and the SAP side, a charge of (¼)VCC voltage in the capacitors C1 and C2 are recycled. Therefore, charges of (½)VCC voltage which is equal to half of the restore voltage to the memory cells are recycled totally, which can reduce the current charged/discharged to the bit lines.
Multiple potential voltages and switches may be provided, which are different from the potential voltages Vm1 and Vm2 so that the potential voltage can be switched at multiple levels (such as n levels). Thus, 1/n power reduction is possible in principle.
The Japanese Laid-Open Patent publication No. 8-249885 discloses a VCC precharge method and a VSS precharge method in addition to the (½)VCC precharge method with respect to equalizing voltage of bit lines. However, margins for reading out respective data “1” and “0” cannot be obtained in case the circuit approach for the precharge voltages is made such that, firstly, stored charges in the cell capacitor are read out on bit lines, next, charge re-distribution is made, and after that, differential amplification is applied to charges between complimentary bit lines by a sense amplifier to read out data. In order to obtain the margins for reading out both data “1” and “0”, the equalizing voltage of the bit lines must be middle potential between the VCC and VSS. In a general circuit design, the equalizing voltage is the (½)VCC voltage, which is obtained by shorting a pair of bit lines having voltages Vcc and VSS. This approach is adopted in the circuit configuration diagram shown in FIG. 11. Therefore, in the technology of the related art, shown in FIG. 11, the reduction of current charged/discharged to bit lines is achieved through the charge recycling by assuming the equalizing voltage of (½)VCC.
In the recent mobile apparatus industries, a semiconductor memory device having large capacity is required with the increase in functions mounted therein. The semiconductor memory device has to be implemented in a limited space at a practical price. Therefore, a DRAM or a synchronous DRAM (called SDRAM, hereinafter), which is highly integrated and is inexpensive for each bit, has been adopted in the mobile apparatus. On the other hand, mobile apparatuses, such as a mobile phone and a digital camera tend to be in stand-by mode for a long period of time. Thus, the reduction of the current consumption in stand-by mode is required to the limit in order to improve the successive useable time characteristic when the battery is driven. Therefore, required is the reduction of the current consumed by refresh operations such as a self-refresh operation, which are performed at intervals of a certain period of time even in stand-by mode in a DRAM, for example.
However, in the circuit configuration diagram (FIG. 11) showing the technology of the related art, the amount of recycled charges is (½)VCC, which is half of the VCC voltage. The reduction effect of the current consumption is limited to ½ of the current consumption relating to current charged/discharged to bit lines of all consumed current involved in refresh operations. That is, the reduction effect of the current consumption is obtained partially, and more reduction is not possible.
Two capacitors C1 and C2 having two voltages of a High-side voltage Vm1 and a Low side voltage Vm2 are connected to a pair of the drive lines SAP and /SAN, respectively, of the sense amplifier so that the pair of bit lines in the cell array 0 is differential-amplified. Here, in order to charge/discharge to the substantial High side voltage Vm1 and the substantial Low side voltage Vm2 for each half number of bit lines, the capacitors C1 and C2 must have larger enough capacitance value than the total stray capacitance value CB of the half number of bit lines. Each cell array must have two capacitors having large capacitance, which may not be achieved in a realistic die size.
In addition, it has been known that the current consumption can be reduced to 1/n in principle by switching the potential voltage in n levels. However, a capacitor and a switch are required for each potential voltage in order to supply current to each potential voltage. In order to switch the n-levels of potential voltages sequentially, a capacitor is required for each potential voltage in the SAP side and the /SAN side. Thus, 2n capacitors having large capacitance are required, which may not be achieved in a realistic die-size.
The current consumed by the refresh operation occupies a large ratio of the current consumption in stand-by mode. A long refresh cycle is required by improving the data holding characteristic so as to reduce the current consumption in stand-by mode. Here, the data holding characteristic is reduced with the passage of time because the stored charges of the high-level voltage accumulated in the cell capacitor leaks. Data holding time tREF is defined as the time when the high-level voltage of the cell capacitor is reduced gradually and goes under the equalizing voltage of the bit line due to the leak. When the cell capacitor and the bit line are connected after the expiration of the data holding time tREF, inversion data may be amplified. Thus, the refresh operation must be performed before the expiration of the data holding time tREF.
If the data holding time tREF can be increased, the refresh cycle can be also increased. Thus, the current consumption involved in the refresh operation can be reduced. In order to increase the data holding time tREF, assuming that the voltage for writing data “1” into the cell capacitor is not varied, the equalizing voltage of the bit lime must be reduced. However, in the technology of the related art, when the SAP of voltage (¾)VCC and the /SAN of the voltage (¼)VCC are shorted by an equalizing signal /EQL0, the equalizing voltage of the bit line is fixed to (½)VCC. As a result, the equalizing voltage of the bit line cannot be reduced.
Here, when it is attempted to shift the bit line to much lower voltage value after the bit line is equalized to the voltage (½)VCC, the bit line voltage must be discharged. As a result new current consumption is caused, which is converse to the reduction of current consumption. Assuming that the equalizing voltage can be set to lower voltage than (½)VCC, the charge recycling operation is not performed properly during the next access operation.
Since a large memory capacity needs to be implemented in a limited space in a mobile apparatus, finer and highly integrated DRAM, for example, is attempted. Thus, the cell size must be reduced, which may deteriorates the data holding time tREF due to leaking, for example. The equalizing voltage for the bit line must be reduced in order to improve the data holding time tREF, which is not possible in the technology of the related art. This is problematic.